The present invention relates to a read-channel circuitry of data read from a mass memory support such as a DVD or a CD and more in particular to an integrated system for decoding according to the Reed-Solomon algorithm data read from a mass memory support coded according to standard DVD-ROM, DVD-R, DVD-RAM or CD-ROM protocols.
DVD and CD optical supports are more and more used for storing large quantities of data in PC""s, digital audio and video playback systems and the like. The storing and reading of data to and from these supports imply the coding and decoding of data according to standard protocols that are defined at international level (e.g. ISO/IEC, CEI/IEC, etc.).
In write-read channel circuitry, reliability in terms of ability of detecting and correcting errors, especially during a phase of decoding of the coded data read from the support during a reading phase, and speed are of paramount importance. Obvious cost-effectiveness considerations call for the highest level of integration of system and/or subsystem circuitries in the minimum number of distinct integrated circuits. Multifunctional Reed-Solomon decoders, capable of handling either DVD decoding and correction or CIRC decoding and correction for all the commonly used CD-modes should be advantageously integrated in a single device including-an embedded RAM required for the decoding and correction operations on a bitstream of input data as produced by the data aquisition means of the read channel.
An architectural layout of such a multifunctional decoder ECC-IC is depicted in FIG. 1.
The integrated decoder handles CD modes bitstreams of any format as well as DVD-ROM, DVD-RAM and DVD-R mode bitstreams and advantageously should possess speed capabilities of handling bitstreams equivalent to a significantly large multiple of standard or base CD rates and of standard or base DVD rates.
With reference to the functional diagram of FIG. 1, the multifunctional integrated decoder ECC-IC, when operating in DVD mode, performs horizontal and vertical decoding of the input data stream and the decoded data are then descrambled and EDC checked before sending them to an output interface circuitry. When operating in a CD mode, the data are decoded and deinterleaved without performing any C3 decoding. Finally, when functioning in a BCA mode, the integrated decoder may perform a Burst Cutting Area decoding of the data stream.
The input data stream consists of the signals output by a data aquisition IC as depicted in FIG. 2. The signals contain data, information about the data and address information.
byte_clk [1]
The byte_clk (byte clock) signal indicates that the data byte can be read. It is generated once per data byte for 1 system clock cycle.
erasure [1]
The erasure bit is set to 1 if the current data byte is not a valid 16/8 modulation pattern (14/8 for CD)xe2x80x94if the pattern is valid, erasure is set to 0.
data [8]
The 8-bit data bus contains the demodulated data byte.
SID [4]
The 4-bit SID (sector ID) contains the 4 least significant bits of the logical sector ID. This signal provides the sector address within each block.
id_error [1]
An id_error bit of 0 indicates that the SD was decoded with no errors and no corrections. If the SID contained errors (no correction possible) or if a single error was corrected, the id_error bit is set to 1.
DVD/BCA frame_address[4:0] or CD S0/S1
In DVD modes the acquisition part keeps a memory of the syncs received and from this history extract the 5-bit frame address.
In BCA mode frame_address[3:0] depends from the sync found (SBBCA, RSBCA1, . . . , RSBCAn, RSBCA13, RSBCA14, RSBCA15).
In CD mode the S0 and S1 signals are sent on frame_address[0] and frame_address[1] respectively.
CD nxfr [1] or DVD next_frame[1]
The DVD next_frame indicates that a new DVD frame is starting. The CD nxfr signal indicates that a new CD frame is starting. The BCA next_frame indicates that a BCA Re-sync has been found.
The timing diagrams of the input data aquisition for the case of operation in DVD mode and in CD mode are shown in FIGS. 3 and 4, respectively.
ECC-IC has two kinds of output interface: one for CD-modes (serial) and one for DVD-modes (parallel). In particular, the CD output interface may be a common I2 S interface employing a format as depicted in FIG. 5, and the subcode interface has as format as depicted in FIG. 6.
The Reed-Solomon decoder block depicted in FIG. 7, supports five main modes:
The number of erasures that can be corrected is programmable, depending on the mode, from 13 up to 16 for DVD Outer, from 7 up to 10 for DVD Inner, from 1 up to 4 for CD C2. The Reed-Solomon block can be programmed to make a severe check for xe2x80x9cmiscorrectionsxe2x80x9d: This preselection will cause a reduction of the decoding performance.
The complete algebraic decoding algorithm for the errors and the erasures is summarized in the following steps:
STEP 1. Calculation of the syndrome S(z), the erasure locator polynomial E(z) and the calculation of the modified syndrome T(z). If r(x) is the received code word       S    j    =            ∑              i        =        0                    n        -        1              ⁢          xe2x80x83        ⁢                  r                  n          -          1                    ⁢              α        ji            
If xcex1jk is the position of a k-erasure and e is the number of erasures       E    ⁢          (      z      )        =            ∏              k        =        1            e        ⁢          xe2x80x83        ⁢          (              1        -                  z          ⁢                      xe2x80x83                    ⁢                      α            jk                              )      
If t is the maximum number of errors the code is able to correct
T(z)=S(z)E(z)mod(z2t)
STEP 2. Perform the extended Euclidean Algorithm (modified version) to calculate the error locator polynomial "sgr"(z) and the error evaluator polynomial xcfx89(z). Calculation of the new error locator polynomial xcexa8(z)
xcexa8(z)="sgr"(z)E(z)
STEP 3. Perform the Chien search to find the roots of the new error locator polynomial. The roots of this polynomial indicate the error and erasure positions in a received code word. Perform the Forney""s algorithm to find the error and erasure values.
STEP 4. Check the decoding process and correct the received code word.
The timing control block sets the control inputs of the Reed-Solomon block and send start syndrome pulse (start_synd) with the first symbol of the code word.
The en_synd is acting as an enable for the data bus (data_in).
Every erasure should be flagged by erasure_pos. During the shifting of the code word, the Reed-Solomon calculates its syndrome and its erasure polynomial.
Once the code word is completely shifted into the Reed-Solomon, the controller has to start the Key Equation Solver (start_kes).
The Reed-Solomon responds when error and location values are ready for the controller (kesready).
The errors and error locations are stored in a Lifo and the controller can read them with read_pos and read_error signals.
The Reed Solomon processing consists of three main tasks:
a) syndrome and erasure polynomial calculation (invoked by start_synd)
b) key equation solving and error calculation (invoked by start_kes)
c) Chien and Forney (generating the ending signal kes_ready)
as depicted in the block diagram of FIG. 8.
In DVD Outer decoding, the erasure polynomial is equal for each column, because it is calculated using the incorrectable flag coming from the Inner decoding. For this reason it is calculated only once for each Ecc block of data at the beginning of the vertical decoding process; the resulting polynomial is stored depending on the store_eras_poly signal. This is depicted by way of a block diagram in FIG. 9.
During the DVD decoding process (Inner-Outer-Inner-Outer- . . . ) the signal sel_eras_poly send to Key Equation Solver the current erasure polynomial (Inner) or the previous stored erasure polynomial (Outer).
To overcome the intrinsic low speed of embedded DRAMs it has been found that a considerable increase of the required processing speed capabilities in a fully integrated decoder (ECC-IC) may be obtained by organizing the data flow within the integrated decoder and the embedded RAM in a way as to reduce the number of accesses to the embedded RAM needed to perfom the decoding at the required speed while using the Reed-Solomon decoding block at twice the maximum clock frequency allowed by the embedded RAM (25 MHz).
Accordingly, in DVD decoding, the syndrome engine is made capable to process two code words at the same time, by storing the final polynomials into distinct registers: two for storing vertical syndromes and one for storing horizontal syndromes, thus implementing a kind of parallel processing in the decoding phase.
Accordingly, in CD decoding, a new addressing scheme has been found to perform very high speed M2 deinterleaving, minimizing the number of accesses to the embedded DRAM required to perform the deinterleaving of data.
The embedded DRAM is organized in distinct banks, each divided into a number of pages of certain capacity of words, functioning in a synchronous page mode.